10.4.7 Clock Gating
Figure 10.7 shows the synergistic effect of applying clock gating to a cluster that supports compiler controlled datapaths. Compiler controlled datapaths provide energy reduction by decreasing datapath activity and avoiding register file and SRAM accesses. To implement it, the load enable signal of each pipeline register should be controlled by software. Since compiler controlled data flow demands circuits with software controlled pipeline register enable signals, it is a trivial extension to clock gate pipeline registers using the same signals. It is seen in the graph that on average this saves 39.5% power when compared to the implementation without clock gating. These results are affected by two factors: a) SRAM power adds a large constant factor to both the cases and, b) Multicycle datapaths like the FPUs are not clock gated because of limitations of the CAD tools. Further reduction is possible by clock gating multicycle datapaths.