2.2 Image and Neural Processors

Neuromorphic system design pioneered by Carver Mead is a method of building electronic circuits inspired by biological systems. For example, Boahen and colleagues at the University of Pennsylvania designed the Visio 1, a chip that models photo-receptors and the four major ganglion cell types found in a retina [15]. This low power chip uses networks of ganglion cells to detect edges and distinguish directions of motion. Harrison and Koch at the California Institute of Technology built a chip that integrated photo-detectors and analog motion detectors to model the first three layers of the visual system of a house fly [45]. They successfully used this chip to steer the direction of an autonomous mobile robot in real time. While there are distinct power and performance advantages to such neuromorphic chips, their analog nature, limited reconfigurability and tight integration with photo-detectors make them unlikely candidates for integration into low power digital computers for perception.

The Xetal processor developed by researchers at Philips Research labs takes the approach of providing a low power programmable linear array of processors designed to accept digital video data [57]. Xetal consists of an array of 320 programmable processing elements that are laid out with communication channels and optimized to process $640\times480$ images at 30 frames per second. This processor is optimized for low power high performance computations like convolution, color conversion, noise reduction, template matching and image compression. No information is currently available on applying Xetal to perception processing.

Fang, a researcher from NASA JPL, describes a low power system on chip design that combines an on-chip camera with a neural net processor and a control microprocessor [34]. This system developed for real-time vision applications in space exploration was reported to be capable of functions like edge detection, connected component detection, motion estimation, etc. Actual power and performance results are not available.

The Simpil processor designed at Georgia Tech is a focal plane SIMD architecture for early vision applications like edge detection, image convolution and compression [24]. In Simpil, up to 16 pixels may be sampled by a SIMD node using A/D conversion and processed locally. Arrays of nodes perform localized computations over the entire focal plane. Estimated total power consumption for a $64\times64$ array of SIMD nodes fabricated in a 0.35$\mu$ process as four separate chips was 5.1 W while operating at 20 MHz.

Binu Mathew