2.6 Distinguishing Features
The perception processor is unique in its use of semiautonomous distributed address generators and scratch-pad memories to efficiently deliver data to a cluster of execution units. Like the perception processor, the Imagine Stream Processor and its successor, the Streaming Super Computer are targeted at stream computing. However, they target high performance optimizations for multimedia and scientific calculations and are less concerned with power efficiency. The perception processor, on the other hand, targets power efficient acceleration of speech recognition and vision applications. Compiler controlled dataflow is used as a means to mimic custom ASICs, but unlike the transport triggered MOVE architecture, the perception processor is operation triggered. Unlike prior research, the fine-grain compiler controlled clock gating described in this dissertation is used not only as a power saving method but also as a means to let software control the lifetime of values held in pipeline registers. This leads to the ability to schedule variables in both time and space and harvest the natural register renaming that happens when a pipeline shifts. Traditional VLIW processors like the Intel Itanium use a rotating register file to accelerate loops. In contrast to traditional architectures, the perception processor uses a mechanism called array variable rotation to create the equivalent of multiple virtual rotating registers, one per array variable accessed in a loop body. Most importantly, an architecture level analysis and optimization of perception applications and a power efficient, yet programmable architecture designed for a variety of stream oriented perception and DSP algorithms is the distinguishing mark of this dissertation.